Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM).
As microprocessor speeds continue to increase, memories have to keep pace. Synchronous memories have done so with high clock speeds as well as pipelined data architectures. Pipelined architectures are typically used to divide the data path into multiple, shorter segments in order to achieve higher clock speeds. However, the higher the clock frequency, the faster the required data access time.
Pipelined architecture also increases the read latency. For example, a three stage data pipeline can accommodate read latencies of up to three clock cycles. The final stage determining the data access time for the read latency of three clock cycles.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to decrease data access time in a memory device having a pipeline architecture.